Modern integrated circuits typically use core devices located in a low-voltage domain to save power and increase processing speed. As technology advances, the power supply voltage for the low-voltage domain continues to decrease. But these same devices use legacy input/output (I/O) standards that require higher power supply voltages. The devices in the low power domain must thus interface through level shifters to the I/O buffers using these higher-voltage legacy I/O standards.
The decreasing power supply voltage used in the low-voltage domains increases the input-to-output voltage range requirement for the corresponding level shifters. For example, it may be necessary to shift from a low-voltage-domain power supply voltage of approximately 0.7 V to an I/O power supply voltage of 1.8 V using a latch-based level shifter. Like any latch, a latch-based level shifter includes a pair of cross-coupled inverters. Each inverter is formed from a serial stack of a PMOS transistor and an NMOS transistor. At any given time, one of the PMOS transistors in the latch-based level shifter will be on. An NMOS access transistor having its gate controlled by the low-voltage domain input signal being shifted must be able to shut down this switched-on PMOS transistor.
Transistors in the low-voltage domain may use a relatively thin gate-oxide layer because of the reduced stress from the lower power supply voltage. In contrast, transistors in a high-voltage power domain such as used for I/O devices require a thicker gate-oxide layer due to the increased stress from the higher power supply voltage. The NMOS access transistors in a latch-based level-shifter are thus thick gate-oxide devices as they are exposed to the I/O power supply voltage. Although each NMOS access transistor is powered by the low-voltage domain input signal, its overdrive is relatively weak as it is driven by the low-voltage-domain power supply voltage. For example, if the NMOS access transistor has a threshold voltage of 400 millivolts, the overdrive is just 300 millivolts for a low-voltage-domain power supply voltage of 0.7 V. Given this weak overdrive, the NMOS access transistors must thus be relatively large so that they can flip the state of the latch in the latch-based level shifter. Accordingly, conventional latch-based level shifters have poor density, particularly at the increased voltage conversion ranges required for level-shifting from modern low-voltage power supply voltages to legacy I/O power supply voltages. Moreover, conventional latch-based level shifters suffer from power consumption issues due to the crowbar circuit current from the power supply node to ground that is discharged while the NMOS access transistor overcomes the inverter's switched-on PMOS transistor.
Accordingly, there is a need in the art for improved latch-based level shifters having improved density and lower power consumption.